ADDER AND SUBTRACTOR USING VERILOG

 
To verify the half adder, full adder, half subtractor, full subtractor using truth table, if-else and combining the 2 half adder to form full adder and 2 half subtractors to form full subtractor.

Software Used: Vivado Software (HLx Editions)

Theory:

Half Adder:

An adder is a digital circuit that performs the addition of numbers. The half adder adds two binary digits called as augend and addend and produces two outputs as the sum and carry; XOR is applied to both inputs to produce the sum and AND gate is applied to both inputs to produce carry. The full adder adds 3 one-bit numbers, where two can be referred to as operands and one can be referred to as bit carried in. And produces 2-bit output, and these can be referred to as output carry and sum.

Truth Table for Half Adder:

A	B	SUM	CARRY
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Truth Table for Full Adder:

A	B	C	SUM	CARRY
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

 

Half Subtractor:

A half subtractor subtracts two 1-bit binary numbers to give two outputs, difference and borrow. Since it neglects any borrow inputs and essentially performs half the function of a subtractor, it is known as the half subtractor. 

 

Truth Table for Half Subtractor:

A	B	DIFFERENCE	BORROW
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

 

Full Subtractor:

A full subtractor accounts for the borrow that a half subtractor neglects. Hence it has three inputs and two outputs. 

Truth Table for Full Subtractor:

A	B	C	DIFFERENCE	BORROW
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Half Adder:

Module Code for Half Adder:

`timescale 1ns / 1ps

module halfnew(a,b,s,c);

input a,b;

output s,c;

xor gate(s,a,b);

and gate1(c,a,b);

endmodule

 

Test Bench Code for Half Adder:

`timescale 1ns / 1ps

module halftest5();

reg a,b;

wire s,c;

halfnew n(a,b,s,c);

initial begin

a=0;b=0;#10;

a=0;b=1;#10;

a=1;b=0;#10;

a=1;b=1;

end

endmodule

 

Fig 1: Simulated Half Adder

Fig 2: Schematic Diagram of Half Adder

Half Subtractor:

Module Code for Half Subtractor:

`timescale 1ns / 1ps

module halfnew(a,b,d,B);

input a,b;

output d,B;

wire w;

xor gate(d,a,b);

not gate2(w,a);

and gate3(B,w,b);

endmodule

Test Bench Code for Half Subtractor:

`timescale 1ns / 1ps

module halftest5();

reg a,b;

wire B,d;

halfnew n(a,b,B,d);

initial begin

a=0;b=0;#10;

a=0;b=1;#10;

a=1;b=0;#10;

a=1;b=1;

end

endmodule

Fig 3: Simulated Half Subtractor

Fig 4: Schematic Diagram of Half Subtractor

Full Adder:

Module Code for Full Adder:

`timescale 1ns / 1ps

module halfnew(a,b,c,S,C);

input a,b,c;

output S,C;

wire w1,w2,w3;

xor gate(w1,a,b);

xor gate1(S,w1,c);

and gate2(w2,w1,c);

and gate3(w3,a,b);

or gate4(C,w2,w3);

endmodule

 

 

Test Bench Code for Full Adder:

`timescale 1ns / 1ps

module halftest5();

reg a,b,c;

wire S,C;

halfnew n(a,b,c,S,C);

initial begin

a=0;b=0;c=0;#10;

a=0;b=0;c=1;#10;

a=0;b=1;c=0;#10;

a=0;b=1;c=1;#10;

a=1;b=0;c=0;#10;

a=1;b=0;c=1;#10;

a=1;b=1;c=0;#10;

a=1;b=1;c=1;

end

endmodule

 

Fig 5: Simulated Full Adder

Fig 6: Schematic Diagram of Full Adder

Half Adder with if-else:

Module Code for Half Adder:

`timescale 1ns / 1ps

module halfadder4(input a, b, output reg s, c);

always@(a or b)

begin

if (a == 0 && b == 0)

begin

s = 0;

c = 0;

end

else if (a == 1 && b == 1)

begin

s = 0;

c = 1;

end

else

begin

s = 1;

c = 0;

end

end

endmodule

 

Test Bench Code for Half Adder:

`timescale 1ns / 1ps

module halftest5();

reg a, b;

wire s, c;

halfadder4 dut (a,b,s,c);

initial

begin

a = 1'b0;b = 1'b0;

#10;

a = 1'b0;b = 1'b1;

#10;

a = 1'b1;b = 1'b0;

#10;

a = 1'b1;b = 1'b1;

end

endmodule

Fig 7: Simulated Half Adder

 

Fig 8: Schematic Diagram of Half Adder

 

HALF SUBTRACTOR WITH IF ELSE:

Module Code for Half Subtractor:

`timescale 1ns / 1ps

module halfadder4(input a, b, output reg B, c);

always@(a or b)

begin

if (a == 0 && b == 1)

begin

B = 1;

c = 1;

end

else if (a == 1 && b == 0)

begin

B = 1;

c = 0;

end

else

begin

B = 0;

c = 0;

end

end

endmodule

Test Bench Code for Half Subtractor:

`timescale 1ns / 1ps

module halftest5();

reg a, b;

wire B, d;

halfadder4 dut (a,b,B,d);

initial

begin

a = 1'b0;b = 1'b0;#10;

a = 1'b0;b = 1'b1;#10;

a = 1'b1;b = 1'b0;#10;

a = 1'b1;b = 1'b1;

end

endmodule

Fig 9: Simulated Half Subtractor

Fig 10: Schematic Diagram of Half Subtractor

Full adder with if-else:

Module Code for Full Adder:

`timescale 1ns / 1ps

module halfadder4(input a, b,c, output reg S, C);

always@(a or b or c)

begin

 

if (a == 0 && b == 0 && c==0)

begin

S = 0;

C = 0;

end

 

if (a == 0 && b == 0 && c==1 )

begin

S = 1;

C = 0;

end

 

if (a == 1 && b == 0 && c==0 )

begin

S = 1;

C = 0;

end

if ( a == 0 && b == 1 && c==0 )

begin

S = 1;

C = 0;

end

 

if (a == 0 && b == 1 && c==1)

begin

S = 0;

C = 1;

end

if ( a == 1 && b == 0 && c==1 )

begin

S = 0;

C = 1;

end

if (a == 1 && b == 1 && c==0 )

begin

S = 0;

C = 1;

end

else if (a == 1 && b == 1 && c==1 )

begin

S = 1;

C = 1;

end

end

endmodule

 

 

Test Bench Code for Full Adder:

`timescale 1ns / 1ps

module halftest5();

reg a, b,c;

wire S, C;

halfadder4 dut (a,b,c,S,C);

initial

begin

a = 1'b0;b = 1'b0;c = 1'b0;#10;

a = 1'b0;b = 1'b0;c = 1'b1;#10;

a = 1'b0;b = 1'b1;c = 1'b0;#10;

a = 1'b0;b = 1'b1;c = 1'b1;#10;

a = 1'b1;b = 1'b0;c = 1'b0;#10;

a = 1'b1;b = 1'b0;c = 1'b1;#10;

a = 1'b1;b = 1'b1;c = 1'b0;#10;

a = 1'b1;b = 1'b1;c = 1'b1;#10;

end

endmodule

 

Fig 11: Simulated Full Adder

Fig 12: Schematic Diagram of Full Adder

FULL SUBTRACTOR WITH IF ELSE:

Module Code for Full Subtractor:

`timescale 1ns / 1ps

module halfadder4(input a, b,c, output reg d, B);

always@(a or b or c)

begin

if (a == 0 && b == 0 && c==0)

begin

d = 0;

B = 0;

end

 

if (a == 0 && b == 0 && c==1 )

begin

d = 1;

B = 1;

end

 

if (a == 1 && b == 0 && c==0 )

begin

d = 1;

B = 0;

end

if ( a == 0 && b == 1 && c==0 )

begin

d = 1;

B = 1;

end

 

if (a == 0 && b == 1 && c==1)

begin

d = 0;

B = 1;

end

if ( a == 1 && b == 0 && c==1 )

begin

d = 0;

B = 0;

end

if (a == 1 && b == 1 && c==0 )

begin

d = 0;

B = 0;

end

else if (a == 1 && b == 1 && c==1 )

begin

d = 1;

B = 1;

end

end

endmodule

Test Bench Code for Full Subtractor:

`timescale 1ns / 1ps

module halftest5();

reg a, b,c;

wire d, B;

halfadder4 dut (a,b,c,d,B);

initial

begin

a = 1'b0;b = 1'b0;c = 1'b0;#10;

a = 1'b0;b = 1'b0;c = 1'b1;#10;

a = 1'b0;b = 1'b1;c = 1'b0;#10;

a = 1'b0;b = 1'b1;c = 1'b1;#10;

a = 1'b1;b = 1'b0;c = 1'b0;#10;

a = 1'b1;b = 1'b0;c = 1'b1;#10;

a = 1'b1;b = 1'b1;c = 1'b0;#10;

a = 1'b1;b = 1'b1;c = 1'b1;#10;

end

endmodule

Fig 13: Simulated Full Subtractor

Fig 14: Schematic Diagram of Full Subtractor

Combination of 2 Half Adder to form Full Adder:

Module Code 1:

module halfadder(a,b,S,C);

input a,b;

output S,C;

xor gate(S,a,b);

and gate1(C,a,b);

endmodule

 

 

Module Code 2:

module full_adder(a,b,c,S,C);

input a,b,c;

output S,C;

wire s1,c1,c2;

halfadder gate1(.S(s1),.C(c1),.a(a),.b(b));

halfadder gate2(.S(S),.C(c2),.a(s1),.b(c));

or gate3(C,c1,c2);

endmodule

 

 

Test Bench Code:

module fullaajnew();

reg a,b,c;

wire S,C;

full_adder n(a,b,c,S,C);

initial begin

a=0;b=0;c=0;#10;

a=0;b=0;c=1;#10;

a=0;b=1;c=0;#10;

a=0;b=1;c=1;#10;

a=1;b=0;c=0;#10;

a=1;b=0;c=1;#10;

a=1;b=1;c=0;#10;

a=1;b=1;c=1;

end

endmodule

Fig 15: Simulated Diagram of 2 Half Adder

Fig 16: Schematic Diagram of 2 Half Adder

Combination of 2 Half Subtractor to form Full Subtractor:

Module Code 1:

module halfsub(a,b,B,D);

input a,b;

output B,D;

wire n;

xor gate(D,a,b);

not gate2(n,a);

and gate1(B,n,b);

endmodule

 

Module Code 2:

module full_adder(a,b,c,B,D);

input a,b,c;

output B,D;

wire s1,c1,c2;

halfsub gate1(.D(s1),.B(c1),.a(a),.b(b));

halfsub gate2(.D(D),.B(c2),.a(s1),.b(c));

or gate3(B,c1,c2);

endmodule

 

Test Bench Code:

module fullaajnew();

reg a,b,c;

wire B,D;

full_adder n(a,b,c,B,D);

initial begin

a=0;b=0;c=0;#10;

a=0;b=0;c=1;#10;

a=0;b=1;c=0;#10;

a=0;b=1;c=1;#10;

a=1;b=0;c=0;#10;

a=1;b=0;c=1;#10;

a=1;b=1;c=0;#10;

a=1;b=1;c=1;

end

endmodule

 

Fig 17: Simulated Diagram of 2 Half Subtractor to form Full Subtractor

 

Fig 18: Schematic Diagram of 2 Half Subtractor to form Full Subtractor

Conclusion:  Half Adder, Full Adder, Half Subtractor, Full Subtractor, the combination of 2 half adder to form full adder and the combination of 2 half subtractors to form full subtractor is studied from the truth table, simulated Diagram, and Schematic Diagram.

Observations:

1. When created a test bench we wrote a = 1'b0 means a is a one-bit having binary that has a value 0. If we want to consider more than one bit this is the best logic for writing.

2. For creating the 2-half adder and then full adder from them we require 2 source file if we try with by creating one source file and taking the output of 1^st Half adder as wire and then giving to second-half adder it gives an error.

3. There is a difference in Schematic Diagram of Adder and Subtractor with Logic Gate concept and with if-else concept, with if-else it becomes complex as mux comes into picture.