LOGIC GATES USING VERILOG

To study logic gates using vivado software.  

Software Used: Vivado Software (HLx Editions)

Theory:

Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of HDL designs.

Logic gates are the basic building blocks of any digital system. It is an electronic circuit having one or more than one input and only one output. The relationship between the input and the output is based on a certain logic. Based on this, logic gates are named as AND gate, OR gate, NOT gate. And we have 2 universal gates NOR AND NAND.

Module Code for OR gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

assign c=a||b;

endmodule

 

Fig 1: Simulated OR Gate

 

 

Fig 2: Schematic Diagram of OR gate

 

Module Code for AND gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

assign c=a & b;

endmodule

 

Fig 3: Simulated AND Gate

 

Fig 4: Schematic Diagram of AND Gate

 

Module Code for NAND gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

nand a1(c,a,b);

endmodule

 

Fig 5: Simulated NAND gate

 

Fig 6: Schematic Diagram of NAND gate

 

Module Code for NOR gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

nor a1(c,a,b);

endmodule

 

Fig 7: Simulated NOR Gate

 

Fig 8: Schematic Diagram of NOR gate

 

Module Code for XOR gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

xor a1(c,a,b);

endmodule

 

Fig 9: Simulated XOR Gate

 

Fig 10: Schematic Diagram of XOR gate

 

Module Code for XNOR gate

‘timescale 1ns /1ps

module orgate_1(a,b,c);

input a,b;

output c;

xnor a1(c,a,b);

endmodule

Fig 11: Simulated XNOR Gate

 

Fig 12: Schematic Diagram of XNOR gate

Module Code for All gates

 ‘timescale 1ns /1ps

module or_gate2();

reg a,b;

wire c;

orgate_1 mayank(a,b,c);

initial begin

a=0;

b=0;

#10

a=0;

b=1;

#10

a=1;

b=0;

#10

a=1;

b=1;

end

endmodule

Module Code for NOT GATE

module orgate_1(a,c);

input a;

output c;

not a1(c,a);

endmodule

 

Test Bench Code for NOT Gate

module or_gate2();

reg a,b;

wire c;

orgate_1 mayank(a,b,c);

initial begin

a=0;

#10

a=1;

end

endmodule

Fig 13: Simulated NOT Gate

 

Fig 14: Schematic Diagram of NOT gate

Conclusion:

All logic gates are studied and schematic Diagrams are also plotted using the software.