To verify the 2x1, 4x1, 8x1 and combination of two 4x1 into 8x1 multiplexer and 1x2,1x4, 1x8 and combination of two 1x4 into 1x8 demultiplexer using if-else condition.

Software Used: Vivado Software (HLx Editions)

Theory:

A multiplexer is a combinational circuit that provides single output but accepts multiple data inputs. A demultiplexer is a combinational circuit that takes single input but that input can be directed through multiple outputs. It performs parallel to serial conversion.

Multiplexer acts as a data selector thus provide a single output from several inputs. However, the demultiplexer acts as a data distributor and generates several outputs with a single input.

Program:

2x1 MUX: Module Code:

`timescale 1ns / 1ps

module mux_1(input a,b,s,output reg y);

always@(s,a,b)

begin

if(s==0)

begin

y=a;

end

else if(s==1)

begin

y=b;

end

endmodule

Test Bench Code:

module mux_2();

reg a,b,s;

wire y;

mux_1 t(a,b,s,y);

initial

begin

s=1'b0;a=1'b0;b=1'b0;#10;

s=1'b0;a=1'b0;b=1'b1;#10;

s=1'b0;a=1'b1;b=1'b0;#10;

s=1'b0;a=1'b1;b=1'b1;#10;

s=1'b1;a=1'b0;b=1'b0;#10;

s=1'b1;a=1'b0;b=1'b1;#10;

s=1'b1;a=1'b1;b=1'b0;#10;

s=1'b1;a=1'b1;b=1'b1;#10;

end

endmodule

Fig 1: Simulated 2x1 MUX

4x1 MUX: Module Code:

module mux_1(input a,b,c,d,s1,s2,output reg y);

always@(s1,s2,a,b,c,d)

begin

if(s1==0 && s2==0)

begin

y=a;

end

else if(s1==0 && s2==1)

begin

y=b;

end

else if(s1==1 && s2==0)

begin

y=c;

end

else if(s1==1 && s2==1)

begin

y=d;

end

endmodule

Test Bench Code:

module mux_2();

reg a,b,c,d,s1,s2;

wire y;

mux_1 t(a,b,c,d,s1,s2,y);

initial

begin

s1=1'b0;s2=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;#10;

s1=1'b0;s2=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b1;#10;

s1=1'b0;s2=1'b0;a=1'b0;b=1'b0;c=1'b1;d=1'b0;#10;

s1=1'b0;s2=1'b0;a=1'b0;b=1'b1;c=1'b1;d=1'b1;#10;

s1=1'b0;s2=1'b0;a=1'b1;b=1'b1;c=1'b0;d=1'b0;#10;

s1=1'b0;s2=1'b1;a=1'b1;b=1'b1;c=1'b0;d=1'b1;#10;

s1=1'b1;s2=1'b1;a=1'b1;b=1'b0;c=1'b1;d=1'b0;#10;

s1=1'b1;s2=1'b1;a=1'b1;b=1'b0;c=1'b1;d=1'b1;#10;

s1=1'b1;s2=1'b1;a=1'b0;b=1'b0;c=1'b0;d=1'b0;#10;

s1=1'b1;s2=1'b1;a=1'b0;b=1'b1;c=1'b0;d=1'b1;#10;

s1=1'b1;s2=1'b0;a=1'b0;b=1'b1;c=1'b1;d=1'b0;#10;

s1=1'b1;s2=1'b0;a=1'b0;b=1'b1;c=1'b1;d=1'b1;#10;

end

endmodule

Fig 2: Simulated 4x1 MUX

8x1 MUX Module Code:

`timescale 1ns / 1ps

module mux_3(input s1,s2,s3,a,b,c,d,e,f,g,h, output reg y);

always@(s1,s2,s3,a,b,c,d,e,f,g,h)

begin

if(s1==0 && s2==0 && s3==0)

begin

y=a;

end

else if(s1==0 && s2==0&& s3==1)

begin

y=b;

end

else if(s1==0 && s2==1&& s3==0)

begin

y=c;

end

else if(s1==0 && s2==1&& s3==1)

begin

y=d;

end

if(s1==1 && s2==0 && s3==0)

begin

y=e;

end

else if(s1==1 && s2==0&& s3==1)

begin

y=f;

end

else if(s1==1 && s2==1&& s3==0)

begin

y=g;

end

else if(s1==1 && s2==1&& s3==1)

begin

y=h;

end

endmodule

Test Bench Code:

`timescale 1ns / 1ps

module mux_4();

reg a,b,c,d,e,f,g,h,s1,s2,s3;

wire y;

mux_3 t(a,b,c,d,e,f,g,h,s1,s2,s3,y);

initial

begin

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;e=1'b0;f=1'b0;g=1'b0;h=1'b0;#10;

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;e=1'b0;f=1'b0;g=1'b0;h=1'b1;#10;

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;e=1'b0;f=1'b0;g=1'b1;h=1'b0;#10;

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;e=1'b0;f=1'b1;g=1'b1;h=1'b1;#10;

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b0;e=1'b1;f=1'b1;g=1'b0;h=1'b0;#10;

s1=1'b0;s2=1'b0;s3=1'b0;a=1'b0;b=1'b0;c=1'b0;d=1'b1;e=1'b1;f=1'b1;g=1'b0;h=1'b1;#10;

end

endmodule

Fig 3: Simulated 8x1 MUX

8x1 mux using two 4x1mux and 2x1:

Module 1 Code:

module twomux(s,b,a,z);

input b,a,s;

output reg z;

always@(s,b,a)

begin

if(s==0)

begin

z<=a;

end

else

if(s==1)

begin

z<=b;

end

endmodule

Module 2 Code:

module fourmux1(s1,s0,d,c,b,a,y1);

input s1,s0,d,c,b,a;

output reg y1;

always@(s1,s0)

begin

if(s1==0&&s0==0)

begin

y1<=a;

end

else

if(s1==0&&s0==1)

begin

y1<=b;

end

else

if(s1==1&&s0==0)

begin

y1<=c;

end

else

if(s1==1&&s0==1)

begin

y1<=d;

end

endmodule

Module 3 Code:

module muxprasad(s2,s1,s0,h,g,f,e,d,c,b,a,y);

input s2,s1,s0,h,g,f,e,d,c,b,a;

output y;

wire p,q;

fourmux1 z0(.y1(p),.s1(s1),.s0(s0),.d(h),.c(g),.b(f),.a(e));

fourmux1 z1(.y1(q),.s1(s1),.s0(s0),.d(d),.c(c),.b(b),.a(a));

twomux z2(.z(y),.s(s2),.b(p),.a(q));

endmodule

Test bench:

module Module_tb();

reg s2,s1,s0,h,g,f,e,d,c,b,a;

wire y;

muxprasad w(s2,s1,s0,h,g,f,e,d,c,b,a,y);

initial begin

s2=0;s1=0;s0=0;h=1;g=1;f=1;e=1;d=1;c=1;b=1;a=0;#10

s2=0;s1=0;s0=1;h=1;g=1;f=1;e=1;d=1;c=1;b=0;a=1;#10

s2=0;s1=1;s0=0;h=1;g=1;f=1;e=1;d=1;c=0;b=1;a=1;#10

s2=0;s1=1;s0=1;h=1;g=1;f=1;e=1;d=0;c=1;b=1;a=1;#10

s2=1;s1=0;s0=0;h=1;g=1;f=1;e=0;d=1;c=1;b=1;a=1;#10

s2=1;s1=0;s0=1;h=1;g=1;f=0;e=1;d=1;c=1;b=1;a=1;#10

s2=1;s1=1;s0=0;h=1;g=0;f=1;e=1;d=1;c=1;b=1;a=1;#10

s2=1;s1=1;s0=1;h=0;g=1;f=1;e=1;d=1;c=1;b=1;a=1;

end

endmodule

Fig 4: Simulated 8x1 using two 4x1 MUX

Fig 4: Schematic diagram of 8x1 using two 4x1 Mux

DEMUX 1x2: Module Code:

`timescale 1ns / 1ps

module dmux_1(input a,s,output reg y0,y1);

always@(s,a)

begin

if(s==0)

begin

y0=a;

y1=0;

end

else if(s==1)

begin

y1=a;

y0=0;

end

endmodule

Test Code:

`timescale 1ns / 1ps

module dmux_2();

reg a,s;

wire y0,y1;

dmux_1 t(a,s,y0,y1);

initial

begin

s=0;a=0;#10;

s=0;a=1;#10;

s=1;a=0;#10;

s=1;a=1;#10;

end

endmodule

Fig 5: Simulated 1x2 DEMUX

DEMUX 1x4: Module Code

`timescale 1ns / 1ps

module dmux_1(input a,s0,s1,output reg y0,y1,y2,y3);

always@(s0,s1,a)

begin

if(s1==0 && s0==0)

begin

y0=a;y1=0;y2=0;y3=0;

end

else if (s1==0 && s0==1)

begin

y0=0;y1=a;y2=0;y3=0;

end

else if(s1==1 && s0==0)

begin

y0=0;y1=0;y2=a;y3=0;

end

else if(s1==1 && s0==1)

begin

y0=0;y1=0;y2=0;y3=a;

end

endmodule

Test Code:

`timescale 1ns / 1ps

module dmux_2();

reg a,s0,s1;

wire y0,y1,y2,y3;

dmux_1 t(a,s0,s1,y0,y1,y2,y3);

initial

begin

s1=0;s0=0;a=1;#10;

s1=0;s0=1;a=1;#10;

s1=1;s0=0;a=1;#10;

s1=1;s0=1;a=1;#10;

end

endmodule

Fig 5: Simulated 1x4 DMux

DEMUX 1x8 Module Code:

`timescale 1ns / 1ps

module dmux_1(input a,s0,s1,s2,output reg y0,y1,y2,y3,y4,y5,y6,y7);

always@(s0,s1,s2,a)

begin

if(s2==0 && s1==0 && s0==0)

begin

y0=a;y1=0;y2=0;y3=0;y4=0;y5=0;y6=0;y7=0;

end

else if (s2==0 && s1==0 && s0==1)

begin

y0=0;y1=a;y2=0;y3=0;y4=0;y5=0;y6=0;y7=0;

end

else if(s2==0 && s1==1 && s0==0)

begin

y0=0;y1=0;y2=a;y3=0;y4=0;y5=0;y6=0;y7=0;

end

else if(s2==0 && s1==1 && s0==1)

begin

y0=0;y1=0;y2=0;y3=a;y4=0;y5=0;y6=0;y7=0;

end

else if(s2==1 && s1==0 && s0==0)

begin

y0=0;y1=0;y2=0;y3=0;y4=a;y5=0;y6=0;y7=0;

end

else if(s2==1 && s1==0 && s0==1)

begin

y0=0;y1=0;y2=0;y3=0;y4=0;y5=a;y6=0;y7=0;

end

else if(s2==1 && s1==1 && s0==0)

begin

y0=0;y1=0;y2=0;y3=0;y4=0;y5=0;y6=a;y7=0;

end

else if(s2==1 && s1==1 && s0==1)

begin

y0=0;y1=0;y2=0;y3=0;y4=0;y5=0;y6=0;y7=a;

end

endmodule

Test Bench Code:

`timescale 1ns / 1ps

module dmux_2();

reg a,s0,s1,s2;

wire y0,y1,y2,y3,y4,y5,y6,y7;

dmux_1 t(a,s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7);

initial

begin

s2=0;s1=0;s0=0;;a=1;#10;

s2=0;s1=0;s0=1;a=1;#10;

s2=0;s1=1;s0=0;a=1;#10;

s2=0;s1=1;s0=1;a=1;#10;

s2=1;s1=0;s0=0;;a=1;#10;

s2=1;s1=0;s0=1;a=1;#10;

s2=1;s1=1;s0=0;a=1;#10;

s2=1;s1=1;s0=1;a=1;#10;

end

endmodule

Fig 6: Simulated 1x8 DEMUX

1x8 using 1x4 and 1x2 DEMUX:

Module 1:

`timescale 1ns / 1ps

module dmux_4(input I7,s3,output reg y0,y1);

always@(I7,s3)

begin

if(s3==0)

begin

y0=I7;

y1=0;

end

else if(s3==1)

begin

y1=I7;

y0=0;

end

endmodule

Module 2:

`timescale 1ns / 1ps

module dmux_3(input I1,s0,s1,output reg y2,y3,y4,y5);

always@(s0,s1,I1)

begin

if(s1==0 && s0==0)

begin

y2=I1;y3=0;y4=0;y5=0;

end

else if (s1==0 && s0==1)

begin

y2=0;y3=I1;y4=0;y5=0;

end

else if(s1==1 && s0==0)

begin

y2=0;y3=0;y4=I1;y5=0;

end

else if(s1==1 && s0==1)

begin

y2=0;y3=0;y4=0;y5=I1;

end

endmodule

Module 3:

`timescale 1ns / 1ps

module dmux_1(I,s3,s1,s0,y2,y3,y4,y5,y6,y7,y8,y9);

input I,s3,s1,s0;

output y2,y3,y4,y5,y6,y7,y8,y9;

wire a,b;

dmux_4 t(.y0(a),.y1(b),.I7(I),.s3(s3));

dmux_3 t1(.y2(y2),.y3(y3),.y4(y4),.y5(y5),.s1(s1),.s0(s0),.I1(a));

dmux_3 t2(.y2(y6),.y3(y7),.y4(y8),.y5(y9),.s1(s1),.s0(s0),.I1(b));

endmodule

Test Bench Code:

module dmux_2();

reg I,s0,s1,s3;

wire y2,y3,y4,y5,y6,y7,y8,y9;

dmux_1 t(I,s0,s1,s3,y2,y3,y4,y5,y6,y7,y8,y9);

initial

begin

s0=0;s1=0;s3=0;;I=1;#10;

s0=0;s1=0;s3=1;I=1;#10;

s0=0;s1=1;s3=0;I=1;#10;

s0=0;s1=1;s3=1;I=1;#10;

s0=1;s1=0;s3=0;;I=1;#10;

s0=1;s1=0;s3=1;I=1;#10;

s0=1;s1=1;s3=0;I=1;#10;

s0=1;s1=1;s3=1;I=1;#10;

end

endmodule

Fig 5: Simulated diagram of 1x8 using two 1x4 DEMUX

Fig 8: Schematic diagram of 1x8 using two 1x4 DEMUX

Conclusion:

Hence Mux and DEMUX is Studied and Simulated Diagram and Schematic Diagram is plotted.

Observations:

1. 1.If we have to do 8x1 mux using 2 4x1 and 1 2x1, we cannot do in one source file using the wire command it gives error so we need to create 3 source file 1 for 4x1, other for 2x1, and others for combining all files together.

2. 2.Our output depends on how we write in always bracket command if the variable which is used first is written in last it gives incorrect results.

Elite Engineer Official

To verify the 2x1, 4x1, 8x1 and combination of two 4x1 into 8x1 multiplexer and 1x2,1x4, 1x8 and combination of two 1x4 into 1x8 demultiplexer using if-else condition.

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MULTIPLEXER AND DEMULTIPLEXER

To verify the 2x1, 4x1, 8x1 and combination of two 4x1 into 8x1 multiplexer and 1x2,1x4, 1x8 and combination of two 1x4 into 1x8 demultiplexer using if-else condition.

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